The present application relates generally to computer system performance analysis. More specifically, the present application is directed to generation of processor stressmarks in a computer system through design space reduction.
In computer system design, understanding of energy behavior and microarchitecture characteristics early in a design process can enable designers to make packaging and power delivery decisions. Further optimizations to a design can be made to effectively manage heat and potential noise issues associated with different stressmarks. A stressmark refers to a condition or set of conditions that puts a desired type of stress on a system, such as a low power condition, a high power condition, a high inductive noise condition, and the like. For example, a particular instruction or sequence of instructions can result in a maximum condition for a metric of interest, a minimum for a metric of interest, or a maximum rate of change of a metric of interest.
When processor performance analysis is attempted manually, the process is typically tedious, time-consuming, and error-prone. Due to the vast number of configuration possibilities for a targeted processor, manual analysis is typically unable to fully explore a solution-space. Systems that apply a generic or brute-force approach to processor analysis are typically constrained by execution time due to the large number of possible configurations and permutations. Expert-defined design spaces can reduce processor analysis computational burden but typically require substantial manual intervention as well as substantial effort by experts to study the processor and configuration options in great detail.